Current Mode Logic (CML), or Emitter-Coupled Logic (ECL) is commonly utilized in high-speed logic (e.g., bipolar digital) circuits. In general, CML/ECL is based on a simple differential amplifier, wherein a transistor(s) (e.g., BJT) is utilized to provide a current to a transistor pair of the differential amplifier. The current can be steered through the transistors by providing bias signals to the bases of the transistors, wherein one signal is utilized to turn an associated transistor “on” and the other signal is utilized to turn the other transistor “off.” The current in the “on” transistor generates a voltage drop across a collector resistor, which can be accessed through an associated output terminal. Since current does not flow through the collector resistor in the “off” transistor, the potential at the associated output terminal is ground potential.
Reversing base signals alternates this effect. Thus, the transistor in the “on” state is switched “off” and the transistor in the “off” state is switched “on.” It is understood that the terms “off” and “on” are not absolute; an “off” device can still pass a small amount of current and an “on” device can carry a large amount of current. A commonly used ratio of “on” current to “off” current in a differential transistor pair switch is in the range of 1000:1 to 10:1. As a consequence, current ceases to flow in one transistor, dropping the associated output voltage at the collector or drain to ground, and commences the flow of current in the other transistor, which generates a voltage drop across the associated collector or drain resistor and provides an output voltage at the associated output terminal. Thus, in this example, current can be steered through the transistors by selectively activating one transistor while deactivating the other transistor. The foregoing provides a means to selectively turn “on” one of the transistors to vary a differential output that can be utilized to drive various logic gates.
The aforementioned principles can be utilized to construct complex gates (e.g., AND, OR, XOR, XNOR, MUX, etc.), including data latches. For example, a data latch can be generated by coupling two differential transistor pairs, wherein one differential transistor pair can be utilized for “tracking” data and the other differential transistor pair can be utilized for “holding” data. By connecting data latches in series, a Data flip-flop (D flip-flop), can be generated. In many instances, the D flip-flop can employ edge triggering (e.g., rising edge triggering (e.g., 0-1 transition) or falling edge triggering (e.g., 1-0 transition)), wherein a rising/falling edge of a clock pulse can be utilized to “latch” data that is present on an input line of the D flip-flop. If the data on the input line changes state while the clock pulse is high/low, then the output follows the input.
Data flip-flops (DFFs) are commonly utilized as building blocks of many integrated circuits such as registers and frequency dividers. The speed of a D flip-flop, and thus many integrated circuits, depends at least in part on the switching time of the differential transistor pairs and the elements that steer the current into the differential transistor pairs. Commonly, the steering elements are differential transistor pairs that provide a clock signal, alternately turning on the “track” and “hold” differential pair. A critical parameter of the D flip-flop is the “clock to Q time,” which is the time between the rising/falling edge of the clock signal to the rising/falling time of the signal at the collectors of the differential transistor pairs in a slave latch and its buffer, which generally follows the differential transistor pairs providing buffering to satisfy the required fanout. The reference edge typically is defined as the point in time wherein the differential signals cross and is also known as the common mode signal voltage.
In D flip-flops, where the differential transistor pairs in the latches carry the data, the clock differential transistor pairs are “stacked” in series with the latch differential transistor pairs. In this configuration, the clock signal switches the clock differential transistor pairs and then the data carrying differential transistor pairs. The summation of propagation delays in both differential transistor pairs is commonly referred to as the total “clock to Q” delay. This total “clock to Q” delay is a measure of performance; and, reducing either or both components (the clock differential transistor pair delay and/or the data differential transistor pair delay) of the total “clock to Q” delay can increase performance (e.g., speed).
As circuit frequency increases, transistor (e.g., a clocking transistor) gain typically decreases. At frequencies over 20 GHz, generally, it becomes difficult to drive transistors and fanout is limited. Conventionally, multiple clock drivers are utilized to drive transistors at high frequencies; however, this solution can be inefficient and increases power dissipation and design layout area.